Blue glowing high energy plasma field in space, computer generated abstract background
Uncategorized

Future Memory Technology

Dean Klein, VP of Memory System Development at Micron, gave the Thursday keynote at ISC ’11 last week. He spoke about future memory technologies with an emphasis on what will be required for exacscale HPC systems.

I had often heard that memory consumes roughly half the power in a typical system. While I realize that reading data objects smaller than cache lines still results in an entire cache line being transferred from memory, which wastes both system bandwith and power, I did not realize that the nature of DRAM designs causes a similar issue (called “overfetch”) at a lower level in which up to 256 times more DRAM bits than have been requested from the part are lit up, which also wastes significant power.

With this as background, Klein talked about HMC (Hybrid Memory Cube), Micron’s design for solving some of the problems associated with DDR3. HMC moves much of the memory control logic onto the part and includes a set of vertically stacked memory modules (four in the first version and more subsequently) with about 1000 TSVs (through-silicon vias) for communication and for cooling. With test parts in the lab, Micron believes  they can deliver 10X bandwidth and 4X-8X the density of DDR3 at a fraction of the power cost. They see HMC as a technology that could be valuable from the exascale all the way down to the mobile market.

Klein also gave his view of what the memory hierachy will look like in the future. It was interesting to hear a memory vendor state that HDDs will remain in the hierarchy rather than being replaced by solid state devices. In Klein’s view, the disk drive vendors will be producing 15-30 TB drives over the next several years and there will continue to be a need for those devices.  His version of the hierarchy looks like this:

Klein’s Memory Hierarchy
HDD
NAND
NVMx
“Far” DRAM
HMC DRAM
L3
L2
L1
CPU

Okay, so while he still sees HDD playing a role, it is true that he does see four levels of solid state memory in the future. 🙂 And while he believes NAND (Flash) will remain an important part of the hierarchy for the next 5-6 years, he also believes it will be eclipsed by some other non-volatile memory technology (NVMx) due to NAND problems, chiefly the fact that NAND endurance decreases as feature sizes decrease. The move from SLC (single-level cell) to MLC (multi-level (2) cell) to TLC (triple-level cell) will also play a factor in this. With respect to NVMx, he mentioned several promising technologies currently being explored within the memory community, none of which I managed to capture in my notes.

Comments

Leave a Reply

Your email address will not be published. Required fields are marked *