I’m in Fiuggi, Italy this week teaching a four-lecture course on Virtualization and High Peformance Computing as part of the Eighth International Summer School on Advanced Computer Architecture for High Performance and Embedded Systems (ACACES 2012). I have about 70 students in the class, primarily from European countries. My first lecture was a whirlwind, high-level overview of High Performance Computing from both a technical and market perspective. Among the topics we covered were the primary programming models used in HPC as well as the major software and hardware components needed to build most mainstream HPC cluster systems. We also discussed some of the pain points currently plaguing HPC as foreshadowing for the discussion about virtualized HPC in the lectures later this week.
The 2nd lecture was an introduction to system-level virtualization. I covered the evolution of x86 virtualization starting with VMware’s binary translation (BT) mechanism which later morphed into a more conventional trap and emulate approach for handling CPU virtualization once the processor vendors added support to correctly handling deprivileged OS execution including x86 ISA oddities. We then briefly discussed several memory-related technologies, including shadow page tables, extended/nested page table support, transparent page sharing, ballooning, swapping, and compression.
Between questions and the content I presented, I wasn’t able to cover the other major virtualization components I had intended to present in the 2nd lecture — live migration, networking, HA, DRS, FT, etc. Happily, I have two more lectures and should be able to finish the virtualization overview tomorrow before moving on to discuss the real topic at hand — use of virtualization for HPC.
It’s been a rewarding experience so far — lots of good questions from the students during class and lots of good conversations outside of class, including at this afternoon’s poster session which included more than 50 submissions.
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